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Liang QI

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Liang QI
祁亮 Liang QI
Year of Graduation: Sep 2019
Ph.D. Dissertation: Low-power cascaded delta-sigma modulator for wideband telecommunication applications
Current Appointment: Assistant Professor in the Shanghai Jiao Tong University, Shanghai, China
  1. Liang Qi, Scientific and Technological R&D Award (Master Student), Macau Science and Technology Award 2016

    FDCT

     Apr-2016
  1. Dongyang Jiang; Sai-Weng Sin; Liang Qi; Guoxing Wang; Rui P. Martins, Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs

    IEEE Open Journal of the Solid-State Circuits Society

     Vol.1, pp. 129-139 Oct-2021
  2. Dongyang Jiang; Liang Qi; Sai-Weng Sin; Franco Maloberti; Rui P. Martins, A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation

    IEEE Journal of Solid-State Circuits

     Vol.56, No 8, pp. 2375-2387 Aug-2021
  3. Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance

    IEEE Journal of Solid-State Circuits

     vol. 55, No. 2, pp. 344-355 Mar-2020
  4. Liang Qi, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH ΔΣ Modulator With Multirate Opamp Sharing

    IEEE Transactions on Circuits and Systems I - Regular Papers

     Vol. 64 , Issue: 10, pp 2641 - 2654 Oct-2017
  5. Liang Qi, Sai Weng Sin, Seng-Pan U, R. P. Martins, Resolution-enhanced sturdy MASH delta–sigma modulator for wideband low-voltage applications

    IET, ELECTRONICS LETTERS, Vol. 51, No. 14, pp. 1061–1063

     Jul-2015
  1. Ran Zhang, Ka-Fai Un, Mingqiang Guo, Liang Qi, Dengke Xu, Weibing Zhao, R. P. Martins, Franco Maloberti and Sai-Weng Sin, A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation

    IEEE International Symposium on Circuits and Systems (ISCAS)

     May-2024
  2. Ke Li, Xianyu Congzhou, Liang Qi, Mingqiang Guo, Rui P. Martins and Sai-Weng Sin, A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering

    IEEE Custom Integrated Circuits Conference (CICC)

     Apr-2024
  3. Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, Guoyong Shi, Guoxing Wang, Advances in Continuous-time MASH ΔΣ Modulators

    2021 IEEE International Conference on ASIC (ASICON)

     Oct-2021
  4. Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

    2020 Symposium on VLSI Circuits Digest of Technical Papers

     Jun-2020
  5. Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ÄÓ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

    CICC 2020

     Mar-2020
  6. Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS

    IEEE International Solid-State Circuits Conference (ISSCC 2019)

     pp.336-338 Feb-2019
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