數據轉換和信號處理

Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

vol.22, no.2, pp.372,383 Feb-2014

Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, A 10.4-ENOB 120MS/s SAR ADC with DAC Linearity Calibration in 90nm CMOS

IEEE Asian Solid-State Circuit Conference – (A-SSCC)

pp 69-72 Nov-2013

Li Ding, WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 13-bit 60M Split Pipelined ADC with Background Gain and Mismatch Error Calibration

IEEE Asian Solid-State Circuit Conference – (A-SSCC),

pp 77-80 Nov-2013

Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS

IEEE Journal of Solid-State Circuits

Vol. 48, Issue 9, pp 2154-2169 Sep-2013

Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Background Gain-Calibration Technique for Low Voltage Pipelined ADCs Based on Nonlinear Interpolation

IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS)

pp 665-668 Aug-2013

Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC

IEEE Journal of Solid-State Circuits

Vol.48, Issue 8, pp 1783-1794 Aug-2013

ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters

Analog Integrated Circuits and Signal Processing, Springer

Vol.76, Issue1, pp 35-46 Jul-2013

U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Cascade Analog to Digital Converting System

Granted Number: 8,466,823

Application Number: 13/198,856

US Patent

Jun-2013