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數據轉換和信號處理

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分類: 數據轉換和信號處理 總計: 250
Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction

IEEE European Solid-State Circuits Conference – ESSCIRC 2016

 pp. 169-172 Sep-2016
Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS

in Journal of Semiconductor Technology and Science

 vol. 16, issue 4, pp. 395-404 Aug-2016
Biao Wang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A high resolution multi-bit incremental converter insensitive to DAC mismatch error

Ph.D Research in Micro-electronics & Electronics (PRIME)

 Jun-2016
Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, An 11b 450 MS/s 3-way Time-Interleaved Sub-ranging Pipelined-SAR ADC in 65nm CMOS

IEEE Journal of Solid-State Circuits

 Volume: 51, Issue: 5, pp. 1223 - 1234 May-2016
Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC

IEEE Journal of Solid-State Circuits

 vol. 51, Issue 2, pp. 365-377 Feb-2016
Jianwei Lui, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

 Issue 24, Issue 7, pp. 2603-2607 Jan-2016
Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation

IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015

 pp.1-4 Nov-2015
Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs

IEEE Transactions on Circuits and Systems I: Regular Papers

 vol.62, no.9, pp.2196-2206 Sep-2015
Liang Qi, Sai Weng Sin, Seng-Pan U, R. P. Martins, Resolution-enhanced sturdy MASH delta–sigma modulator for wideband low-voltage applications

IET, ELECTRONICS LETTERS, Vol. 51, No. 14, pp. 1061–1063

 Jul-2015
Yan Zhu, Chi Hang Chan, Wong, S.-S., Seng-Pan U, R. P. Martins, Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

 Volume:24 , Issue: 3, pp. 1203 - 1207 Jun-2015
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