Sai Weng Sin

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Sai Weng Sin
冼世榮 Sai Weng Sin
副教授
Current Appointment:
Phone: (+853) 8822-8795
Room Number: N21-3007c

For a complete CV, please go to http://www.fst.umac.mo/en/staff/fstsws.html

  1. Chi Hang Chan, Yan Zhu, Yan Lu, Sai Weng Sin, R. P. Martins, 技术发明奖二等奖 (应用于新兴系统具前沿能效的数据及电源转换集成电路设计)

    The Science and Technology Development Fund(FDCT)

    Oct-2020
  2. Seng-Pan U, Yan Zhu, Sai Weng Sin, Chi Hang Chan, 技术发明奖-三等奖(高性能宽带数据转换介面接口-应用于不断发展的微电子信息世界)

    The Science and Technology Development Fund(FDCT)

    Oct-2016
  3. Seng-Pan U, Sai Weng Sin, Yan Zhu, Chi Hang Chan, U-Fat Chio, 技术发明奖二等奖(应用CMOS纳米制程技术的全方位和先进的数据与信号转换芯片平台的研究与开发)

    The Science and Technology Development Fund(FDCT)

    Nov-2014
  4. R. P. Martins, Seng-Pan U, Pui In Mak, Sai Weng Sin, Second Class Award of the Macao Science and Technology Award – Technological Invention category

    The Science and Technology Development Fund

    Oct-2012
  5. Seng-Pan U, Pui In Mak, Sai Weng Sin, Special Award, the Macao Science and Technology Award 2012

    FDCT

    Oct-2012
  6. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Travel Grant Award (A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure)

    2012 IEEE Symposium on VLSI Circuits – VLSI 2012

    Jun-2012
  7. Seng-Pan U, Pui In Mak, Sai Weng Sin, National Science and Technology Progress Awards

    Ministry of Science and Technology of the People's Republic of China

    [First Time in Macau] Jan-2012
  8. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, IEEE A-SSCC Student Design Contest Best Design Award (A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation)

    IEEE Asian Solid-State Circuits Conference

    Nov-2011
  9. Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Bronze Leaf Certificate (A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture)

    IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia)

    Oct-2011
  10. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Silk-Road Award (A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS)

    Digest of Technical Papers from IEEE International Solid-State Circuits Conference – ISSCC 2011

    [Awarded for best asian PhD student research in ISSCC (“World Chip Olympic”)] Feb-2011
  11. U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, Award for Research Excellence 2007-2009

    University of Macau

    Apr-2010
  12. Sai Weng Sin, Seng-Pan U, R. P. Martins, Merit Paper Award (Novel Timing-Skew-Insensitive, Multi-Phase Clock Generation Scheme For Parallel Dac And N-Path Filter)

    The 2006 Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC)

    Apr-2009
  13. Li Ding, Sio Chan, Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, 1st Runner-up (A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique)

    The Institution of Engineering and Technology, Hong Kong (Undergraduate Section - IET Young Members Exhibition and Conference 2008)

    Dec-2008
  14. Li Ding, Sio Chan, Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, Champion in IEEE Project Competitions (A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique)

    IEEE Macau Society

    Nov-2008
  15. Sai Weng Sin, Chipidea Microelectronics Prize – Postgraduate Level, for the outstanding academic and research achievement in Microelectronics

    University of Macau

    Nov-2008
  16. Sai Weng Sin, Chipidea Microelectronics Prize (Generalized Low-Voltage Circuit Design Techniques for Very High-Speed Time-Interleaved Pipelined ADC)

    Chipidea Microelectronics, Macau

    Apr-2008
  17. Sai Weng Sin, Student Paper Contest Award

    International Symposium on Circuits and Systems (ISCAS’2005)

    May-2005
  18. Sai Weng Sin, Seng-Pan U, R. P. Martins, Selected Student Paper Scholarship (Paper Title I: Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits”, Paper Title II: Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits” )

    IEEE International Symposium on Circuits and Systems (ISCAS)

    May-2005
  19. Sai Weng Sin, Excellent Scholarship of CEM (Companhia de Electricidade de Macau) for the outstanding academic achievement

    University of Macau

    Aug-2001
  20. Sai Weng Sin, Excellent Scholarship of Macau Foundation for the outstanding academic achievement

    University of Macau

    Aug-2001
  21. Sai Weng Sin, Excellent Scholarship of HSBC (The Hongkong and Shanghai Banking Corporation) for the outstanding academic achievement

    University of Macau

    Aug-2000
  1. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, Single-Loop Linear-Exponential Multi-Bit Incremental Analog-to-Digital Converter

    No. 10,644,718 B1

    US Patent

    Jul-2020
  2. Man-Chung Wong, Chi-Seng Lam, Yan-Zheng Yang, Wai-Hei Choi, Ning-Yi Dai, Ya-jie Wu, Chi-Kong Wong, Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, Mixed signal controller

    Granted, No. 9,692,232

    US patent

    Jun-2017
  3. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, Analog to Digital Converter Circuit

    Granted Number: 201242261

    Application Number: 100107757

    Taiwan Patent

    Mar-2014
  4. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Delay Generator

    Granted Number: 201246793

    Application Number: 100116148

    Taiwan Patent

    Mar-2014
  5. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Cascade Analog to Digital Converting System

    Granted Number: 8,466,823

    Application Number: 13/198,856

    US Patent

    Jun-2013
  6. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Delay Generator

    Granted Number: 8,441,295

    Application Number: 13/289,229

    US Patent

    May-2013
  7. Sai Weng Sin, He Gong Wei, Li Ding, Yan Zhu, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption

    Granted Number: 8,427,355

    Application Number: 13/232,442

    US Patent

    Apr-2013
  8. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, N-Bits Successive Approximation Register Analog-to-Digital Converting System

    Granted Number: 8,344,931

    Application Number: 13/150,508

    US Patent

    Jan-2013
  1. Wen-Liang Zheng, Yuan Ren, Chi-Seng Lam, Sai Weng Sin, Weng-Keong Che, Ran Ding, R. P. Martins, A 470nA quiescent current and 92.7%/94.7% efficiency DCT/PWM control buck converter with seamless mode transition for IoT application

    IEEE Transactions on Circuits and Systems I - Regular Papers (TCAS-I)

    Accepted Jul-2020
  2. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration

    IEEE Journal of Solid-State Circuits

    vol. 55, Issue 3, pp. 693-705 (invited special issue of CICC) Mar-2020
  3. Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance

    IEEE Journal of Solid-State Circuits

    vol. 55, No. 2, pp. 344-355 Mar-2020
  4. Wen-Ming Zheng, Wen-Liang Zheng, Chi-Wa U, Chi-Seng Lam, Yan Lu, Sai Weng Sin, Man-Chung Wong, R. P. Martins, Analysis, Design and Control of an Integrated Three-Level Buck Converter under DCM Operation

    Journal of Circuits, Systems and Computers

    vol. 29, no. 1, pp. 1-20 Mar-2020
  5. Wen-Ming Zheng, Wen-Liang Zheng, Chi-Wa U, Chi-Seng Lam, Yan Lu, Sai Weng Sin, Man-Chung Wong, R. P. Martins, Analysis, design and control of an integrated three-level buck converter under DCM operation

    Journal of Circuits, Systems, and Computers

    vol. 29, no. 1, 2050011 (20 pages) Jan-2020
  6. U-Fat Chio, Kuo-Chih Wen, Sai Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, R. P. Martins, An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery

    IEEE Journal of Solid-State Circuits

    Vol.54, No.10, pp. 2637-2648 Oct-2019
  7. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS

    IEEE Journal of Solid-State Circuits

    Vol. 54, Issue: 4, pp. 1161-1172 Apr-2019
  8. Da Feng, Edoardo Bonizzoni, J.E.Franca, Sai Weng Sin, R. P. Martins, A 10-MHz Bandwidth Two-Path Third-OrderΣΔModulator With Cross-Coupling Branches

    IEEE Transactions on Circuits and Systems II: Express Briefs

    Vol.65, No. 10, pp 1410 - 1414 Oct-2018
  9. Jiali Ma, Mingqiang Guo, Sai Weng Sin, R. P. Martins, A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current

    IEEE Transactions on Circuits and Systems II: Express Briefs

    Vol.65, No.10, pp 1380 - 1384 Oct-2018
  10. Yu-Jun Mao, Chi-Seng Lam, Sai Weng Sin, Man-Chung Wong, R. P. Martins, Review and Selection Strategy for High-Accuracy Modeling of PWM Converters in DCM

    Hindawi Journal of Electrical and Computer Engineering

    Volume 2018, Article ID 3901693, 16 pages Oct-2018
  11. Wen-Liang Zheng, Chi-Seng Lam, Sai Weng Sin, Franco Maloberti, Man-Chung Wong, R. P. Martins, A 220-MHz bondwire-based fully-integrated KY converter with fast transient response under DCM operation

    IEEE Transactions on Circuits and Systems I - Regular Papers (TCAS-I)

    Accepted Aug-2018
  12. Ya-jie Wu, Chi-Seng Lam, Man-Chung Wong, Sai Weng Sin, R. P. Martins, A reconfigurable and extendable digital architecture for mixed signal power electronics controller

    IEEE Transactions on Circuits and Systems II - Express Briefs (TCAS-II)

    Accepted Jul-2018
  13. Weiwei Qin, Sai Weng Sin, Seng-Pan U, R. P. Martins, Quick and Cost-Efficient A/D Converter Static Characterization using Low-Precision Testing Signal

    Microelectronics Journal - Elsevier

    vol. 74, pp.86-93 Feb-2018
  14. Liang Qi, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH ΔΣ Modulator With Multirate Opamp Sharing

    IEEE Transactions on Circuits and Systems I - Regular Papers

    Vol. 64 , Issue: 10, pp 2641 - 2654 Oct-2017
  15. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC

    in IEEE Transactions on Circuits and Systems I: Regular paper

    Vol.64, Issue 8, pp.1966-1976 Aug-2017
  16. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC

    IEEE Transactions on Circuits and Systems I: Regular paper

    Vol.64, No 7, pp.1684-1695 Jul-2017
  17. Ziyang Luo, Yan Lu, Mo Huang, Junmin Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Sub-1V 78-nA Bandgap Reference with Curvature Compensation

    Elsevier Microelectronics Journal

    vol. 63, pp. 35–40 May-2017
  18. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

    Vol.25, Issue 3, pp.1168-1172 Mar-2017
  19. Jiang DongYang, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Reconfigurable mismatch-free time-interleaved bandpass sigma–delta modulator for wireless communications

    Electronics Letters

    Vol. 53 , Issue: 7, pp 506 - 508 Mar-2017
  20. Yan Lu, Haojuan Dai, Mo Huang, Man-Kay Law, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting

    IEEE Transactions on Circuits and Systems II

    Volume: 64, Issue: 2, pp.166 - 170 Feb-2017
  21. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Boris Murmann, Seng-Pan U, R. P. Martins, Metastablility in SAR ADCs

    press in IEEE Transactions on CAS – Part II: Express Briefs

    Volume: 64, Issue: 2, pp.111 - 115 Feb-2017
  22. Yi-Wei Tan, Chi-Seng Lam, Sai Weng Sin, Man-Chung Wong, Seng-Pan U, R. P. Martins, DCM operation analysis of 3-level boost converters

    ”, IET Electronics Letters

    vol. 53, no. 4, pp. 270 – 272 Feb-2017
  23. Arshad Hussain, Sai Weng Sin, Chi Hang Chan, Seng-Pan U, Franco Maloberti, R. P. Martins, Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

    vol. 25, Issue. 1, pp. 364 – 374 Jan-2017
  24. Mo Huang, Yan Lu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Wing-Hung Ki, Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators

    IEEE Transactions on Circuits and Systems II

    Volume:63 , Issue: 9 , pp.903-907 Sep-2016
  25. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS

    in Journal of Semiconductor Technology and Science

    vol. 16, issue 4, pp. 395-404 Aug-2016
  26. Mo Huang, Yan Lu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Fully-Integrated Digital LDO with Coarse-Fine-Tuning and Burst-Mode Operation

    IEEE Transactions on Circuits and Systems II

    Volume:63 , Issue: 7 , pp. 663-687 Jul-2016
  27. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC

    IEEE Journal of Solid-State Circuits

    vol. 51, Issue 2, pp. 365-377 Feb-2016
  28. Jianwei Lui, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

    Issue 24, Issue 7, pp. 2603-2607 Jan-2016
  29. Wen-Liang Zheng, Chi-Seng Lam, Wen-Ming Zheng, Sai Weng Sin, Ning-Yi Dai, Man-Chung Wong, Seng-Pan U, R. P. Martins, DCM operation analysis of KY converter

    IET Electronics Letters

    vol. 51, no. 24, pp. 2037 – 2039 Nov-2015
  30. Man-Chung Wong, Yan-Zheng Yang, Chi-Seng Lam, Wai-Hei Choi, Ning-Yi Dai, Ya-jie Wu, Chi-Kong Wong, Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, Self-reconfiguration property of a mixed signal controller for improving power quality compensator during light loading

    IEEE Transactions on Power Electronics

    vol. 30, no. 10, pp. 5938 – 5951 Oct-2015
  31. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs

    IEEE Transactions on Circuits and Systems I: Regular Papers

    vol.62, no.9, pp.2196-2206 Sep-2015
  32. Liang Qi, Sai Weng Sin, Seng-Pan U, R. P. Martins, Resolution-enhanced sturdy MASH delta–sigma modulator for wideband low-voltage applications

    IET, ELECTRONICS LETTERS, Vol. 51, No. 14, pp. 1061–1063

    Jul-2015
  33. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Split-SAR ADCs: Improved Linearity with Power and Speed Optimization

    ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems

    Vol.22, Issue: 2 , pp 372 - 383 Feb-2014
  34. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

    vol.22, no.2, pp.372,383 Feb-2014
  35. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS

    IEEE Journal of Solid-State Circuits

    Vol. 48, Issue 9, pp 2154-2169 Sep-2013
  36. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC

    IEEE Journal of Solid-State Circuits

    Vol.48, Issue 8, pp 1783-1794 Aug-2013
  37. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters

    Analog Integrated Circuits and Signal Processing, Springer

    Vol.76, Issue1, pp 35-46 Jul-2013
  38. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, Excess-Loop-Delay Compensation Technique for CT Delta Sigma Modulator with Hybrid Active-Passive Loop-Filters

    Analog Integrated Circuits and Signal Processing, Vol. 76, Issue 1

    May-2013
  39. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

    IEEE Journal of Solid-State Circuits

    Vol.47, Issue 11, pp 2614-2626 Dec-2012
  40. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

    IEEE Journal of Solid-State Circuits

    Vol.47, no11, pp. 2763-2772 Nov-2012
  41. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC

    IEEE Transactions on CAS – Part II: Express Briefs

    vol. 57, Issue 8, pp. 607-611 Aug-2010
  42. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS

    IEEE Journal of Solid-State Circuits

    vol. 45, Issue 6, pp. 1111-1121 Jun-2010
  43. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs

    Hindawi VLSI Design, Special Issue with "Selected Papers from the Midwest Symposium on Circuits and Systems

    vol. 2010, no. 1, pp. 1-8 Apr-2010
  44. Sai Weng Sin, Seng-Pan U, R. P. Martins, A 1.2-V 10-bit 60-360MS/s Time-Interleaved Pipelined ADC in 0.18um CMOS with Minimized Supply Headroom

    IET Proceedings - Circuits, Devices and Systems

    vol. 4, Issue 1, pp. 1-13 Jan-2010
  45. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS

    IEEE Trans. on Circuits and System II – Express Briefs

    vol. 57, Issue 1, pp. 16-20 Jan-2010
  46. Sai Weng Sin, Seng-Pan U, R. P. Martins, A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18um CMOS

    澳門機電工程專業協會(APEMEM)會刊(2007-2008)

    pp. 1-7 Apr-2009
  47. Sai Weng Sin, Seng-Pan U, R. P. Martins, Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps

    IEEE Transactions on Circuits and Systems I - Regular Papers

    vol. 55, Issue 8, pp. 2188 - 2201 Sep-2008
  48. Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch

    IEEE Trans. on Circuits and Systems II – Express Briefs

    vol. 55, Issue 7, pp. 648-652 Jul-2008
  49. Seng-Pan U, Sai Weng Sin, R. P. Martins, Exact Spectra Analysis of Sampled Signals with Jitter-Induced Nonuniformly Holding Effects

    IEEE Transactions on Instrumentation and Measurement

    vol. 53, Issue 4, pp. 1279-1299 Aug-2004
  1. Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

    2020 Symposium on VLSI Circuits Digest of Technical Papers

    Jun-2020
  2. Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ÄÓ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

    CICC 2020

    Mar-2020
  3. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing

    IEEE Symposium on VLSI Circuits (VLSI)

    Jun-2019
  4. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration

    IEEE Custom Integrated Circuits Conference (CICC)

    Apr-2019
  5. Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS

    IEEE International Solid-State Circuits Conference (ISSCC 2019)

    pp.336-338 Feb-2019
  6. U-Fat Chio, Kuo-Chih Wen, Sai Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, R. P. Martins, An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery

    2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    Nov-2018
  7. Jianyang Deng, Chi-Seng Lam, Man-Chung Wong, Lei Wang, Sai Weng Sin, R. P. Martins, A Power Quality Indexes Measurement System Platform with Remote Alarm Notification

    44th Annual Conference of the IEEE Industrial Electronics Society (IECON 2018)

    Oct-2018
  8. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, A 550μW 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS

    Proc. IEEE Symposium on VLSI Circuits - VLSI 2018

    Jun-2018
  9. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS

    2018 IEEE Symposium on VLSI Circuits

    [Travel Grant Award] [Invited Special Issue in JSSC] Jun-2018
  10. Yi-Wei Tan, Chi-Seng Lam, Sai Weng Sin, Man-Chung Wong, R. P. Martins, Design and control of an Integrated 3-level boost converter under DCM operation

    2018 International Symposium on Circuits and Systems (ISCAS)

    pp. 1-5 May-2018
  11. Jiaji Mao, Mingqiang Guo, Sai Weng Sin, R. P. Martins, A 14-bit Split Pipeline ADC with Self-Adjusted Opamp-Sharing Duty Cycle

    IEEE International Solid-State Circuits Conference – ISSCC 2018

    Ph.D. Student Research Preview - Session 3, Paper No.7 Feb-2018
  12. U-Fat Chio, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, A 5-bit 2 GS/s binary-search ADC with charge-steering comparators

    IEEE Asian Solid-State Circuits Conference (A-SSCC)

    pp221-224 Nov-2017
  13. Chi-Wa U, Chi-Seng Lam, Man-Kay Law, Sai Weng Sin, Man-Chung Wong, Si-Seng Wong, R. P. Martins, CCM Operation Analysis and Parameter Design of Negative Output Elementary Luo Converter for Ripple Suppression

    The 43rd Annual Conference of the IEEE Industrial Electronics Society (IECON 2017), Beijing, China,

    No. 01, 2017, pp. 4867 - 4871. Oct-2017
  14. Xia Du, Chi-Seng Lam, Sai Weng Sin, Man-Kay Law, Franco Maloberti, Man-Chung Wong, Seng-Pan U, R. P. Martins, A digital pwm controlled ky step-up converter based on frequency domain ΣΔ ADC

    The 26th IEEE International Symposium on Industrial Electronics (ISIE 2017)

    pp.561-564 Jun-2017
  15. Mingqiang Guo, Sai Weng Sin, Seng-Pan U, R. P. Martins, Split-based time-interleaved ADC with digital background timing-skew calibration

    2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    Jun-2017
  16. Wei Li, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Mixed-Signal Sigma-Delta Interface circuit for Navigation System Applications

    International Symposium on Integrated Circuits

    Dec-2016
  17. Yuan Ren, Sai Weng Sin, Chi-Seng Lam, Man-Chung Wong, Seng-Pan U, R. P. Martins, A high DR multi-channel stage-shared hybrid sigma-delta modulator for integrated power electronics controller front-end

    IEEE Asian Solid-State Circuits Conference (A-SSCC)

    Toyama, Japan Nov-2016
  18. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching

    IEEE ISCAS 2017

    accepted Oct-2016
  19. Dante Gabriel Muratore, Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti, U-Fat Chio, Sai Weng Sin, R. P. Martins, An 8-bit 0.7-GS/s Single Channel Flash-SAR ADC in 65-nm CMOS Technology

    . IEEE European Solid-State Circuits Conference – ESSCIRC 2016

    pp. 421-424 Sep-2016
  20. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction

    IEEE European Solid-State Circuits Conference – ESSCIRC 2016

    pp. 169-172 Sep-2016
  21. Biao Wang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A high resolution multi-bit incremental converter insensitive to DAC mismatch error

    Ph.D Research in Micro-electronics & Electronics (PRIME)

    Jun-2016
  22. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation

    IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015

    pp.1-4 Nov-2015
  23. Wen-Ming Zheng, Chi-Seng Lam, Sai Weng Sin, Yan Lu, Man-Chung Wong, Seng-Pan U, R. P. Martins, Capacitive floating level shifter: Modeling and design

    IEEE Region 10 Conference (TENCON)

    Macau, China, pp. 1-6 Nov-2015
  24. Ka-Fai Chan, Chi-Seng Lam, Wen-Liang Zheng, Wen-Ming Zheng, Sai Weng Sin, Man-Chung Wong, Generalized type III controller design interface for dc-dc converters

    The IEEE Region 10 Conference (TENCON 2015)

    Macau, China, pp. 1 – 6 Nov-2015
  25. Haojuan Dai, Yan Lu, Man-Kay Law, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Review and Design of the On-Chip Rectifiers for RF Energy Harvesting

    IEEE International Wireless Symposium (IWS)

    pp. 1-4 Mar-2015
  26. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 12b 180MS/s 0.068mm2 Full-Calibration Integrated Pipelined-SAR ADC

    International Solid State Circuits Conference (ISSCC)

    Student Research Previews Feb-2015
  27. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS

    Solid- State Circuits Conference - (ISSCC)

    (Pre-doctoral achievement awards),pp1-3 Feb-2015
  28. Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors

    IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC)

    pp. 364-365 Feb-2015
  29. Da Feng, Sai Weng Sin, E. Bonizzoni, Franco Maloberti, Time interleaved current steering DAC for ultra-high conversion rate

    IEEE Ph.D Research in Micro-electronics & Electronics (PRIME)

    pp. 1-4 Jun-2014
  30. Li Ding, WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 13-bit 60M Split Pipelined ADC with Background Gain and Mismatch Error Calibration

    IEEE Asian Solid-State Circuit Conference – (A-SSCC),

    pp 77-80 Nov-2013
  31. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Background Gain-Calibration Technique for Low Voltage Pipelined ADCs Based on Nonlinear Interpolation

    IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS)

    pp 665-668 Aug-2013
  32. Yan Du, Tao He, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Continuous-Time VCO-Assisted VCO-Based Sigma Delta Modulator with 76.6dB SNDR and 10MHz BW

    IEEE International Symposium on Circuits and Systems (ISCAS)

    pp 373-376 May-2013
  33. WenLan Wu, Yan Zhu, U-Fat Chio, Li Ding, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 0.6V 8B 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS

    IEEE International Symposium on Circuits and Systems (ISCAS)

    pp 2239-2242 May-2013
  34. Yun Du, Tao He, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Continuous-Time VCO-Assisted VCO-Based ΣΔ Modulator with 76.6dB SNDR and 10MHz BW

    in IEEE International Symposium on Circuits and Systems (ISCAS)

    May-2013
  35. Yun Du, Tao He, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Robust NTF Zero Optimization Technique for Both Low and High OSRs Sigma-Delta Modulators

    IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

    pp 29-32 Dec-2012
  36. Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity

    IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

    pp 33-36 Dec-2012
  37. WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array

    IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

    pp 268-271 Dec-2012
  38. Yun Du, Tao He, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A robust NTF Zero Optimization Technique for both Low and High OSRs Sigma-Delta Modulators

    in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

    Dec-2012
  39. Tao He, Yun Du, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A DT 0–2 MASH ΣΔ Modulator with VCO-Based Quantizer for Enhanced Linearity

    in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

    Dec-2012
  40. Zhijie Chen, Yang Jiang, ChenYan Cai, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application

    IEEE Asian Solid-State Circuit Conference – (A-SSCC)

    pp 257-260 Nov-2012
  41. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC

    IEEE Asian Solid-State Circuit Conference – (A-SSCC)

    pp 153-156 Nov-2012
  42. Zhijie Chen, JIANG Yang, Chenyan Cai, He-Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application

    in IEEE Asian Solid State Circuits Conference (A-SSCC)

    Nov-2012
  43. Guohe Yin, He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 0.024mm2 4.9 fJ 10-Bit 2MS/s SAR ADC in 65 nm CMOS

    IEEE European Solid-State Circuits Conference – ESSCIRC 2012

    pp 377-380 Sep-2012
  44. Rui Wang, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique

    IEEE European Solid-State Circuits Conference – ESSCIRC 2012

    pp 265-268 Sep-2012
  45. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators

    IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2012

    pp 1096-1099 Aug-2012
  46. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC

    IEEE Custom Integrated Circuits Conference – CICC 2012

    pp 1-4 Aug-2012
  47. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators

    in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

    Aug-2012
  48. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC

    2012 Symposium on VLSI Circuits Digest of Technical Papers

    pp 90-91 Jun-2012
  49. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure

    2012 Symposium on VLSI Circuits Digest of Technical Papers

    pp 86-87 Jun-2012
  50. Tao He, Yang Jiang, Yun Du, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer

    IEEE Int. Symposium on Circuits and Systems (ISCAS)

    pp 65-69 May-2012
  51. Tao He, JIANG Yang, Yun Du, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer

    in IEEE International Symposium on Circuits and Systems (ISCAS)

    May-2012
  52. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

    Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic")

    pp. 61-64 Best Student Design Contest Award Nov-2011
  53. Si-Seng Wong, U-Fat Chio, He Gong Wei, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators

    Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic")

    pp. 73-76 Nov-2011
  54. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

    Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic")

    pp. 233-236 Nov-2011
  55. Seng-Pan U, Sai Weng Sin, Yan Zhu, U-Fat Chio, He Gong Wei, R. P. Martins, Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs

    Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011

    pp. 173-176 Nov-2011
  56. Arshad Hussain, Sai Weng Sin, Seng-Pan U, R. P. Martins, Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation

    International SoC Design Conference – ISOCC

    pp. 76-79 Nov-2011
  57. Bo Sun, U-Fat Chio, Chi-Seng Lam, Ning-Yi Dai, Man-Chung Wong, Chi-Kong Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, A FPGA-Based Power Electronics Controller for Hybrid Active Power Filters

    IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia)

    Macao, China, pp. 25-28 Oct-2011
  58. Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture

    Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimaAsia)

    pp. 1-4 Oct-2011
  59. Rui Wang, U-Fat Chio, Chi Hang Chan, Li Ding, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A time-efficient dither-injection scheme for pipelined SAR ADC

    IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia)

    pp. 9-12 Oct-2011
  60. Arshad Hussain, Sai Weng Sin, Seng-Pan U, R. P. Martins, NTF Zero Compensation Technique For Passive Sigma-Delta Modulator

    IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia)

    pp. 82-85 Oct-2011
  61. U-Fat Chio, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration

    ", IEEE European Solid-State Circuits Conference – ESSCIRC 2011

    pp. 363-366 Sep-2011
  62. JIANG Yang, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC

    IEEE Midwest Symposium on Circuits and Systems – MWSCAS

    pp. 1-4 Aug-2011
  63. Zhijie Chen, Peng Zhang, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error

    IEEE Midwest Symposium on Circuits and Systems – MWSCAS

    pp. 1-4 Aug-2011
  64. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time Sigma-Delta Modulators

    IEEE Midwest Symposium on Circuits and Systems – MWSCAS

    pp. 1-4 Aug-2011
  65. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC

    IEEE Midwest Symposium on Circuits and Systems – MWSCAS

    pp. 1-4 Aug-2011
  66. Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range

    IEEE International Midwest Symposium on Circuits and Systems – MWSCAS

    pp. 1-4 Aug-2011
  67. Peng Zhang, Zhijie Chen, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC

    ", IEEE Midwest Symposium on Circuits and Systems – MWSCAS

    pp. 1-4 Aug-2011
  68. Tao He, Yun Du, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range

    in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

    Aug-2011
  69. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time ΣΔ Modulators

    in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

    Aug-2011
  70. Bo Sun, Ning-Yi Dai, U-Fat Chio, Man-Chung Wong, Chi-Kong Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, FPGA-based Decoupled Double Synchronous Reference Frame PLL for Active Power Filters

    2011 6th IEEE Conference on Industrial Electronics and Applications (ICIEA)

    pp. 2145 – 2150 Jun-2011
  71. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS

    IEEE International Solid-State Circuit Conference (ISSCC),

    pp. 188-189 Feb-2011
  72. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators

    IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

    pp. 1011-1014 Dec-2010
  73. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs

    IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

    pp. 208-211 Dec-2010
  74. Guohe Yin, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications

    IEEE International Conference on Electronics, Circuits and Systems (ICECS)

    pp. 878-881 Dec-2010
  75. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators

    IEEE International Conference on Electronics, Circuits and Systems (ICECS

    pp. 547-550 Dec-2010
  76. JIANG Yang, Kim Fai Wong, Chenyan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators

    in IEEE International Conference on Electronics, Circuits and Systems (ICECS)

    pp.547-550 Dec-2010
  77. JIANG Yang, Kim-Fai Wong, Chenyan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators

    in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

    Dec-2010
  78. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation

    IEEE Asian Solid-State Circuits Conference – ASSCC 2010

    pp. 1-4 Nov-2010
  79. Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Digital Background Nonlinearity Calibration Algorithm for Pipelined ADCs

    IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia)

    pp. 115-118 Sep-2010
  80. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H

    in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010

    pp. 218-221 Sep-2010
  81. Si-Seng Wong, U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power Effective 5-bit 600 MS/s Binary-Search ADC with Simplified Switching

    in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010

    pp. 29-32 Aug-2010
  82. Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Threshold-Embedded Offset Calibration Technique for Inverter-Based Flash ADCs

    in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010

    pp. 489-492 Aug-2010
  83. Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, Level-Shifting Variable Current Charging Technique for High-Speed Comparator-Based Switched-Capacitor Circuits

    IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010

    pp. 566-569 Aug-2010
  84. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump

    IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010

    pp. 889-892 Aug-2010
  85. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Background Amplifier Offset Calibration Technique for High-Resolution Pipelined ADC

    IEEE International NEWCAS Conference – NEWCAS 2010

    pp. 41-44 Jun-2010
  86. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs

    IEEE International Symposium on Circuits and Systems – ISCAS 2010

    pp. 607-611 May-2010
  87. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Noise-Insensitive Offset Calibration Technique for Time Interleaved SAR ADC

    Proc. IEEE International Symposium on Circuits and Systems – LASCAS 2010

    Feb-2010
  88. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator

    in Proc. of 2009 International SoC Design Conference (ISOCC)

    pp. 392-395 Nov-2009
  89. Sai Weng Sin, He Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R. P. Martins, Franco Maloberti, On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator

    in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC)

    pp. 49-52 Nov-2009
  90. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Si-Seng Wong, Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs

    in Proc. of 2009 International SoC Design Conference (ISOCC)

    pp. 333-336 Nov-2009
  91. Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Modified Charging Algorithm for Comparator-Based Switched-Capacitor Circuits

    in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS

    pp. 86-89 Aug-2009
  92. U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, Comparator-Based Successive Folding ADC

    IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

    pp. 117-120 Jan-2009
  93. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Process- and Temperature- Insensitive Current-Controlled Delay Generator for Sampled-Data Systems

    in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

    pp. 1192-1195 Dec-2008
  94. Li Ding, Sio Chan, Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique

    in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

    pp. 276-279 Dec-2008
  95. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs

    in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

    pp. 1164-1167 Dec-2008
  96. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs

    in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2008

    pp. 642-645 Sep-2008
  97. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier

    ", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS)

    pp. 5-8 Aug-2008
  98. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

    in Proceedings of IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2008

    pp. 922-925 Aug-2008
  99. Jun-Xia Ma, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 1.8V 1.056GS/s 6-b Flash-Interpolation ADC for MB-OFDM UWB Applications

    Proceedings of RIUPEEEC (Macao, China)

    pp. 105-108 Jul-2006
  100. Sai Weng Sin, Seng-Pan U, R. P. Martins, Novel Timing-Skew-Insensitive, Multi-phase Clock Generation Scheme for Parallel DAC and N-Path Filter

    Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006

    pp. 133-136 Jul-2006
  101. Sai Weng Sin, Seng-Pan U, R. P. Martins, A Novel Low-Voltage Finite-Gain Compensation Technique for High-Speed Reset- and Switched-Opamp Circuits

    in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS)

    pp. 3794-3797 May-2006
  102. Jun-Xia Ma, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power-Efficient 1.056 GS/s Resolution-Switchable 5-bit/6-bit Flash ADC for UWB Applications

    in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

    pp. 4305-4308 May-2006
  103. Sai Weng Sin, Seng-Pan U, R. P. Martins, Novel low-voltage circuit techniques for fully-differential reset- and switched-opamps

    in Proc. of Ph.D. Research In Micro-Electronics & Electronics (PRIME)

    pp. 398-401 Jul-2005
  104. Sai Weng Sin, Seng-Pan U, R. P. Martins, A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits

    in Proc.of IEEE International Symposium on Circuits and Systems (ISCAS)

    vol. 2, pp. 1585-1588 May-2005
  105. Sai Weng Sin, Seng-Pan U, R. P. Martins, A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits

    in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

    vol. 2, pp. 1581-1584 May-2005
  106. Sai Weng Sin, Seng-Pan U, R. P. Martins, Novel Low Jitter Multi-Phase Clock Generation Scheme for Parallel Analog-to-Digital Conversion Systems

    Proc. IEEE/IEEJapan International Analog VLSI Workshop – AVLSIWS 2004

    pp. 172-175 Oct-2004
  107. Sai Weng Sin, Seng-Pan U, R. P. Martins, A Generalized Timing-Skew-Free, Multi-Phase Clock Generation Platform for Parallel Sampled-Data Systems

    in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS)

    vol. 1, pp. I-369 – I-372 May-2004
  108. Seng-Pan U, Sai Weng Sin, R. P. Martins, Spectra Analysis of Nonuniformly Holding Signals for Time-Interleaved Systems with Timing Mismatches

    in Proc. of IEEE Instrumentation and Measurement Technology Conference (IMTC)

    vol. 2, pp. 1298-1301 May-2003
  109. Sai Weng Sin, Seng-Pan U, R. P. Martins, Timing-Mismatch Analysis in High-Speed Analog Front-End with Nonuniformly Holding Output

    in Proc. of IEEE International Symposium on Circuits and Systems 2003 (ISCAS)

    vol. 1, pp. I-129 – I-132 May-2003
  110. Sai Weng Sin, Seng-Pan U, R. P. Martins, Quantitative Noise Analysis of Jitter-Induced Non-Uniformly Sampled-And-Held Signals

    in Proc. of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

    vol. 6, pp. VI_253-VI_256 Apr-2003
  111. Sai Weng Sin, Lai Keng Chong, Chiang Kuok Vai, Choi Wai Wa, K.W.Tam, R. P. Martins, An analytical linearization method for CMOS MMIC power amplifier using Multiple Gated Transistors

    in Proceedings of IEEE International Conference on ASIC - ASICON’2001

    pp. 670-672 Oct-2001
  112. Sai Weng Sin, Lai Keng Chong, Chiang Kuok Vai, Choi Wai Wa, K.W.Tam, R. P. Martins, A New IMD3 Reduction Approach based on Composite Effect of g""m and g""ds,""

    Proceedings of IEEE CAS Workshop on Wireless Communications and Networking, South Bend, Indiana

    Aug-2001
  1. Sai Weng Sin, Seng-Pan U, R. P. Martins, Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters

    Analog Circuits and Signal Processing, Springer

    978-90-481-9709-5 Oct-2010
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