無線IC Archives - 頁28，共30 - University of Macau | State Key Laboratory of Analog and Mixed-Signal VLSI

分類: 無線IC 總計: 292

Pui In Mak, Seng-Pan U, R. P. Martins, A 1V IEEE 802.11a/b/g-Compliant Receiver IF-to-Baseband Chip in 0.35µm CMOS for Low-Cost Wireless SiP

52nd Edition International Solid-State Circuits Conference – ISSCC 2005, San Francisco, USA, February 2005, and 42nd Edition Design Automation Conference – DAC 2005, Anaheim, California, USA, June 2005

Student Design Contest – Second Place, Conceptual Category" – Referred in IEEE Solid-State Circuits Society Newsletter, Vol.10, No.3, pp.7-8 Sep-2005

Pui In Mak, Seng-Pan U, R. P. Martins, A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-/spl mu/m CMOS

in Proc. of IEEE Custom Integrated Circuits Conference (CICC)

pp. 649-652 Sep-2005

Pui In Mak, Seng-Pan U, R. P. Martins, Multistandard-Compliant Receiver Architecture with low-voltage Implementation

in Proc. of Ph.D. Research In Micro-Electronics & Electronics (PRIME)

pp. 223-226 Jul-2005

Pui In Mak, Seng-Pan U, R. P. Martins, Two-Step Channel Selection – A Novel Technique for Reconfigurable Multistandard Transceiver Front-Ends

IEEE Transactions on Circuits and Systems-I, Regular Paper

Vol. 52, issue 7, pp 1302-1315 Jul-2005

Pui In Mak, Seng-Pan U, R. P. Martins, Silver Leaf Certificate (Multistandard-Compliant Receiver Architecture with low-voltage Implementation)

IEEE Ph.D. Research in Microelectronics and Electronics Conference – PRIME'2005

Jul-2005

Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC

in Proc. of Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC)

pp. 276-280 Jun-2005

Ka Hou Ao Ieong, Chong-Yin Fok, Pui In Mak, Seng-Pan U, R. P. Martins, A Frequency Up-Conversion and Two-Step Channel Selection Embedded CMOS D/A Interface

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

vol. 1, pp. 392-395 May-2005

Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, Model, Characterization and Solutions of Unstable Reference Voltage for Very-High-Speed Pipelined A/D Converters

in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

pp. 138-143 Oct-2004

Pui In Mak, Seng-Pan U, R. P. Martins, A Power-and-Area Efficient, Multifunctional CMOS A/D Interface for a Low-IF/Zero-IF Reconfigurable Receiver

", in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

pp. 233-238 Oct-2004

Pui In Mak, Ka Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R. P. Martins, A Complex Low-IF Transceiver Architecture for Relaxing Phase Noise and Settling Time Requirements of RF PLL-FS

in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

pp. 221-226 Oct-2004

發表著作