无线IC

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Chao Fan, Wei-Han Yu, Pui In Mak, R. P. Martins, A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS

IEEE Transactions on Circuits and systems - I

vol. 66, No.12, pp. 4850–4861, Dec-2019
Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS

IEEE Asia Pacific Conference on Circuits and Systems

Nov-2019
Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, Best Paper Award

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Nov-2019
Ka-Meng Lei, Pui-In Mak, Man-Kay Law and R. Martins, Palm-size μNMR relaxometer using a digital microfluidic (DMF) device and a semiconductor transceiver for chemical/biological diagnosis

US10436726B2

US Patents

Oct-2019
Yong Chen, Pui In Mak, Zunsong Yang, Chirn Chye Boon, R. P. Martins, A 0.0071-mm² 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis

IEEE Transactions on Circuits and Systems I: Regular Paper

Vol.66, No.10, pp.3991-4004 Oct-2019
Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, A 0.0018-mm2 153%-Locking-Range CML-Based Divider-by-2 with Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell

IEEE Transactions on Circuits and Systems I: Regular Papers

Vol.66, No. 9, pp 3330-3339 Sep-2019
Jiangchao Wu, Ka-Chon Lei, Hou-Man Leong, JIANG Yang, Man-Kay Law, Pui In Mak, R. P. Martins, Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS

in IEEE Int'l Symposium on IC and Systems (ISICAS)

pp. 1768 - 1772, Venice, Italy Aug-2019
Bing Li, Lingjun Zhang, Mingzhong Li, Shuangpeng Wang, Man-Kay Law, Yingzhou Huang, Weijia Wen, Bingpu Zhou, Suppression of Coffee-ring Effect via Periodic Oscillation of Substrate for Ultra-sensitive Enrichment towards Surface-enhanced Raman Scattering

Nanoscale

Vol.11, Issue 43, pp. 20335-21012 Aug-2019
Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui In Mak, R. P. Martins, Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm

2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

Jul-2019
Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui In Mak, R. P. Martins, Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Vol.27, Issue 10, pp.2223-2236 Jun-2019
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