2022-08-17T15:28:27+08:002022-08-17|新聞與活動, 活動資訊|

The Distinguished Lecture on “Vision Radar: A Stereo Depth Coprocessor with Pixel Level Pipeline and Region Optimized Semi-Global Matching” will take place as follows:

Date: 22 August 2022 (Monday)

Time: 15:00 – 16:00

Venue: To be held online via Zoom (https://umac.zoom.us/j/91332303273?pwd=TGQ0d05WUU9oWGYwTFFVeFM5MUtWdz09)


The speaker is:

Prof. AN Fengwei, Assistant Professor, The School of Microelectronics (SME), Southern University of Science and Technology, Shenzhen, China


The Lecture is:

Vision Radar: A Stereo Depth Coprocessor with Pixel Level Pipeline and Region Optimized Semi-Global Matching



The semi-global matching (SGM) algorithm in stereo vision is a well-known depth-estimation method since it can generate dense and robust disparity maps. However, the real-time processing and low power dissipation, the specifications of the Internet-of-Thing (IoT) applications, are challenging for their computational complexity. This work proposes a hardware-oriented SGM algorithm with pixel-level pipeline and region-optimized cost aggregation for high-speed processing and low hardware-resource usage. Firstly, the matching costs in a region are integrated with an optimization strategy to significantly reduce memory usage and improve the processing speed of the cost aggregation. Then, a two-layer parallel two-stage pipeline architecture, which enables pixel-level processing, is designed to calculate two directions (0° and 135°) aggregation further to solve the crucial computational bottleneck of the SGM algorithm. Finally, the architecture is demonstrated on a low-cost XILINX Spartan-7 device and an advanced Stratix-V FPGA device for VGA (640×480) depth estimation. The experimental results show that the proposed architecture with compact hardware architecture ensures accuracy. The pixel-level pipeline architecture enables a processing speed of 355 frames per second (fps) at 109MHz on the Spartan-7 FPGA device and 508 fps at 156MHz on the Stratix-V FPGA.



Prof. AN Fengwei received his Ph.D. degree in Electronics Engineering from Hiroshima University, Japan, in 2013. From 2013 to 2017, he was also with the Engineering department of Hiroshima University as an Assistant Professor. From 2017 to 2018, he worked as an Associate Professor at Hiroshima University, Japan. Then, he joined Panasonic, developing digital signal processors (DSP) and image signal processors (ISP) for automotive. From 2019, he has been an Associate Professor with the school of Microelectronics (SME), Southern University of Science and Technology, Shenzhen. He has authored/co-authored around 50 peer-reviewed papers in international journals and conferences, including TCSVT, TCAS-I, TCAS-II TVLSI, Sensors, CICC, and A-SSCC. His major research interests include energy-efficient digital image signal processors, ultra-low-voltage circuit design, and Neuromorphic computing.


For more details, kindly find the event poster, abstract and bio.