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Sai Weng Sin, Seng-Pan U, R. P. Martins, Novel Low Jitter Multi-Phase Clock Generation Scheme for Parallel Analog-to-Digital Conversion Systems

Proc. IEEE/IEEJapan International Analog VLSI Workshop – AVLSIWS 2004

 pp. 172-175 Oct-2004
Seng-Pan U, Sai Weng Sin, R. P. Martins, Exact Spectra Analysis of Sampled Signals with Jitter-Induced Nonuniformly Holding Effects

IEEE Transactions on Instrumentation and Measurement

 vol. 53, Issue 4, pp. 1279-1299 Aug-2004
Ngai Kong, Seng-Pan U, R. P. Martins, A Novel Current-Mode Reconfigurable Membership Function Circuit for Mixed-Signal Fuzzy Hardware

Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006

 pp. 101-104 Jul-2004
Pui In Mak, Seng-Pan U, R. P. Martins, Best Paper Award (A Power-and-Area Efficient, Multifunctional CMOS A/D Interface for a Low-IF/Zero-IF Reconfigurable Receiver)

IEEJ (7th) International Analog VLSI Workshop (AVLSIWS 2004)

 Jul-2004
Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, "2nd Prize” in Student Paper Contest (Modeling of Noise Sources in Reference Voltage Generator for Very-High-Speed Pipelined ADC)

IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004)

 Jul-2004
Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, Modeling of Noise Sources in Reference Voltage Generator for Very-High-Speed Pipelined ADC

in Proc. of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

 vol. 1, pp. 5-8 Jul-2004
Kin-Sang Chio, Seng-Pan U, R. P. Martins, A Novel Low-Voltage 2nd-Order Sigma-Delta Modulator with Double-Sampling for GSM/DECT/WCDMA

in Proc. of International Conference on Communications, Circuits and Systems (ICCCAS)

 vol. 2, pp. 1146-1150 Jun-2004
Pui In Mak, Kin-Kwan Ma, Weng Ieng Mok, Chi-Sam Sou, Kit-Man Ho, Cheng-Man Ng, Seng-Pan U, R. P. Martins, An I/Q-Multiplexed and OTA-Shared CMOS Pipelined ADC with an A-DQS S/H Front-End for Two-Step-Channel-Select Low-IF Receiver

in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS)

 vol. 1, pp. 1068-1071 May-2004
Sai Weng Sin, Seng-Pan U, R. P. Martins, A Generalized Timing-Skew-Free, Multi-Phase Clock Generation Platform for Parallel Sampled-Data Systems

in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS)

 vol. 1, pp. I-369 – I-372 May-2004
Pui In Mak, Seng-Pan U, R. P. Martins, A Low-IF/Zero-IF Reconfigurable Receiver with Two-Step Channel Selection Technique for Multistandard Applications

", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

 vol. 4, pp. 417-420 May-2004
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