A 0.096-mm2 1-to-20-GHz Triple-Path Noise-Cancelling Common-Gate Common-Source LNA with Complementary pMOS-nMOS Configuration 2020 1 月 01 | 週三 ...
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector 2020 1 月 01 | 週三 ...
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection 2020 1 月 01 | 週三 ...
Nondestructive and objective assessment of the vestibular function in rodent models: A review 2020 1 月 01 | 週三 ...
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS 2019 12 月 01 | 週日 ...
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS 2019 11 月 01 | 週五 ...
Palm-size μNMR relaxometer using a digital microfluidic (DMF) device and a semiconductor transceiver for chemical/biological diagnosis 2019 10 月 08 | 週二 ...
