Academic Qualifications
- Ph.D. in Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, China (2015)
- M.Sc. in Electrical and Electronics Engineering, Faculty of Science and Technology, University of Macau, China (2011)
- B.Sc. in Electrical and Computer Engineering, University of Washington (Seattle) ,United States (2008)
Professional Experience
State-Key Laboratory of Analog and Mixed-Signal VLSI (AMSV)
- Associate Professor, AMSV, University of Macau (Aug. 2022 – Present)
- Assistant Professor, AMSV, University of Macau (Apr. 2017 – Aug. 2022)
- Research Assistant Professor, AMSV, University of Macau (Jan. 2016 – Mar. 2017)
- Post-doc Follow, AMSV, University of Macau (Aug. 2015 – Dec. 2015)
Others
- Special Scientist, Dept. of EEE, University of California (Mar. 2016 – July. 2016)
Research
Research Interests
- Analog and mixed-signal CMOS integrated circuits
- High speed Nyquist ADC and Wideband SDM (DT and CT)
- Low jitter Ring-VCO-based PLL
- PUF
Teaching Experience
B.Sc. Courses
- Analog Integrated Circuit Design (ECEN3017)
- Advanced Topics in Electrical and Computer Engineering (ECEN8001)
- Design Project (ECEB420)
M.Sc. Courses
- Introduction to Research (ECEN7001)
- Thesis (ECEN7999)
Theses Supervision
LIU JIANWEI | 2011-2016 | Design Techniques for Energy Efficient ADCs |
JIANG WENNING | 2015-present | High performance Nyquist ADC |
WANG GUANCHENG | 2014-2017 | Split DAC mismatch calibration for SAR ADC |
ZHANG WAI HONG | 2015-2018 | Background comparator offset calibration technique |
HO IOK MENG | 2015-2018 | Multi-bit SAR switching techniques |
LEI XUEWEI | 2016-present | Phase ADC |
LI CHENG | 2014-2018 | SAR reference error analysis |
Professional Services
2015-present Reviewer: JSSC, TCAS I, TCAS II, TVLSI
Services at University of Macau
2017-present Cheng Yu Tung College Affiliates
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技术发明奖二等奖 (应用于新兴系统具前沿能效的数据及电源转换集成电路设计)
The Science and Technology Development Fund(FDCT)
Oct-2020 -
技术发明奖二等奖 (促进智慧澳门的模拟与混合信号集成电路设计)
The Science and Technology Development Fund(FDCT)
Oct-2018 -
技术发明奖-三等奖(高性能宽带数据转换介面接口-应用于不断发展的微电子信息世界)
The Science and Technology Development Fund(FDCT)
Oct-2016 -
IEEE SSCS Pre-doctoral Achievement Award 2015
The IEEE Solid-State Circuits Society
Feb-2015 -
技术发明奖二等奖(应用CMOS纳米制程技术的全方位和先进的数据与信号转换芯片平台的研究与开发)
The Science and Technology Development Fund(FDCT)
Nov-2014 -
Scientific and Technological R&D Award (PhD Student), Macau Science and Technology Award 2014
FDCT
Jul-2014 -
Scientific and Technological R&D Award (Master Student)
The Science and Technology Development Fund
Oct-2012 -
Travel Grant Award (A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure)
2012 IEEE Symposium on VLSI Circuits – VLSI 2012
Jun-2012 -
IEEE A-SSCC Student Design Contest Best Design Award (A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation)
IEEE Asian Solid-State Circuits Conference
Nov-2011 -
Chipidea Microelectronics Prize (A Study on Comparator and Offset Calibration Techniques in High Speed Nyquist ADCs)
Chipidea Microelectronics
Oct-2011 -
Silk-Road Award (A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS)
Digest of Technical Papers from IEEE International Solid-State Circuits Conference – ISSCC 2011
[Awarded for best asian PhD student research in ISSCC (“World Chip Olympic”)] Feb-2011 -
Award for Research Excellence 2007-2009
University of Macau
Apr-2010 -
Bronze Leaf Certificate (Comparator-Based Successive Folding ADC)
IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia 2009)
Sep-2009
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Pipelined analogue to digital converter
EP 20157326.8
EUROPEAN (under review)
Jul-2020 -
Sampling front-end for analog to digital converter
Granted Number: 8,947,283
Application Number: 13/915,949
US patent
Feb-2015 -
Analog to Digital Converter Circuit
Granted Number: 201242261
Application Number: 100107757
Taiwan Patent
Mar-2014 -
A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption
Granted Number: 8,427,355
Application Number: 13/232,442
US Patent
Apr-2013 -
N-Bits Successive Approximation Register Analog-to-Digital Converting System
Granted Number: 8,344,931
Application Number: 13/150,508
US Patent
Jan-2013
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A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SABELD-Merged Integrator and 3-Stage Opamp
2020 Symposia on VLSI Technology and Circuits
Jun-2020 -
A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC
forthcoming Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2018
May-2018 -
A 12b 180MS/s 0.068mm2 Full-Calibration Integrated Pipelined-SAR ADC
International Solid State Circuits Conference (ISSCC)
Student Research Previews Feb-2015