Yang JIANG
江洋 Yang JIANG
Year of Graduation:
Jan 2019
Ph.D. Dissertation:
Design of fully integrated fine-grained switched-capacitor DC-DC topologies in bulk CMOS
Current Appointment:
Assistant Professor in the State Key Lab of Analog and Mixed-Signal VLSI, UM, Macao
奖项
Total:0
专利与技术转移
Total:0
期刊和杂志
Total:6
会议报告和简报
Total:3
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An Arithmetic Progression Switched-Capacitor DC-DC Converter with Soft VCR Transitions Achieving 93.7% Peak Efficiency and 400 Ma Output Current
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), Session 2 / Paper 2.1
Nov-2021
书籍及书籍章节
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