Biao Wang - University of Macau | State Key Laboratory of Analog and Mixed-Signal VLSI

奖项 Total:0

专利与技术转移 Total:0

期刊和杂志 Total:1

Hongjiang Chen, Yuhang Peng, Liang Qi, Biao Wang, Sai-Weng Sin, Rui P. Martins and Mingqiang Guo, A 12-Bit 1-Gs/S 5.1-mW Pipelined ADC Using an Open-Loop Floating Inverter Amplifier with Residue-Dependent Integration Time Compensation
IEEE Journal of Solid-State Circuits
vol. 58, Early Access Nov-2025

会议报告和简报 Total:2

Zhensheng Li, Biao Wang, Mingqiang Guo, Rui P. Martins and Sai -Weng Sin, A 103.9dB-SFDR 83.8dB-SNDR 3MHz-BW Multi-Bit Quadratic-Exponential Noise-Coupled IDSM with High Tolerance to DAC Non-Linearity
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Feb-2026
Hongjiang Chen, Yuhang Peng, Liang Qi, Biao Wang, Sai-Weng Sin, Rui P. Martins and Mingqiang Guo, A 12-Bit 1-Gs/S 5.1-mW Pipelined ADC Using an Open-Loop Floating Inverter Amplifier with Residue-Dependent Integration Time Compensation
2025 IEEE European Solid-State Electronics Research Conference (ESSERC)
Sep-2025

书籍及书籍章节 Total:0