The Distinguished Lecture on “Design Efficient AI SoC with Architecture and Circuit Innovations“ will take place as follows:
Date: 08 May 2025 (Thursday)
Time: 10:30 – 12:00
Venue: Research Building N21, G013
The speaker is:
Prof. JIA Tianyu, Assistant Professor, School of Integrated Circuits, Peking University
The Lecture is:
Design Efficient AI SoC with Architecture and Circuit Innovations
Abstract:
The rapid advancement of AI demands highly efficient system-on-chip (SoC) solutions to meet the computational and energy constraints of modern applications. This talk will introduce a few architecture and circuit-level innovations that enable the design of high-performance, energy-efficient AI SoCs. At architecture-level, cutting-edge accelerators will be introduced for generative Diffusion (ISSCC 25), TPU (DATE 25) and multimodal LLMs (DAC 25) leveraging efficient compute-in-memory (CIM) techniques. At circuit-level, we explore novel circuit design approaches, including fine-grained SoC power management solutions for edge SoC (VLSI 24) and AI processor (VLSI 25). By combining architectural enhancements with circuit-level optimizations, designers can achieve significant improvements in performance-per-watt, making AI acceleration feasible for edge devices, data centers, and beyond.
Biography:
Prof. JIA Tianyu is currently an Assistant Professor and Boya Young Fellow at the School of Integrated Circuits, Peking University, China. He was a Postdoctoral Fellow at Harvard University and an Assistant Research Professor at ECE department, Carnegie Mellon University at USA. His research interests include domain-specific architecture, compute-in-memory accelerator, and heterogeneous SoC design. Prof. JIA has published more than 60 papers at top-tiered IC conferences and journals including ISSCC, VLSI, DAC and JSSC. He received the Ph.D. degree in computer engineering from Northwestern University, USA.
For more details, kindly find the event poster, abstract and bio.
