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Xiaoteng Zhao

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Xiaoteng Zhao
趙瀟騰 Xiaoteng Zhao
  1. Xiao Teng ZHAO, Scientific and Technological R&D Award for Postgraduates

    The Science and Technology Development Fund (FDCT)

     Dec-2022
  2. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, Best Paper Award

    IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

     Nov-2019
  1. Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, and Rui P. Martins, A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS

    IEEE Journal of Solid-State Circuits

     vol. 57, no. 5, pp. 1358-1371 May-2022
  2. Xiaoteng Zhao, Yong Chen, Pui-In Mak and Rui P. Martins, A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate FD Pulling off an 8.2-(Gb/s)/µs Acquisition Speed of PAM-4 Input in 28-nm CMOS

    IEEE Journal of Solid-State Circuits

     vol. 57, pp. 546–561 Feb-2022
  3. Xiaoteng Zhao, Yong Chen, Pui-In Mak, R. P. Martins, A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS

    IEEE Transactions on Circuits and Systems I: Regular Papers

     vol. 68, no1, pp. 89-102 Jan-2021
  4. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, A 0.0018-mm2 153%-Locking-Range CML-Based Divider-by-2 with Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell

    IEEE Transactions on Circuits and Systems I: Regular Papers

     Vol.66, No. 9, pp 3330-3339 Sep-2019
  5. Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui In Mak, R. P. Martins, Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     Vol.27, Issue 10, pp.2223-2236 Jun-2019
  6. Yong Chen, Zunsong Yang, Xiaoteng Zhao, Yunbo Huang, A 6.5×7 µm2 0.98-to-1.5 mW Non-Self-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4 to 44 GHz)

    IEEE Solid-State Circuits Letters

     Vol.2, Issue: 5, pp. 37-40 May-2019
  1. Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, and Rui P. Martins, A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS [Best Student Paper Award – 3rd Place]

    IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp 131-134

     Jun-2021
  2. Xiaoteng Zhao, Yong Chen, Xuqiang Zheng, Pui-In Mak, and Rui P. Martins,, A 0.01mm2 1.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase

    IEEE International Microwave Symposium (IMS), pp 386-389

     Jun-2021
  3. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS

    IEEE Custom Integrated Circuits Conference (CICC)

     Mar-2020
  4. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS

    IEEE Asia Pacific Conference on Circuits and Systems

     Nov-2019
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