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He Gong WEI

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He Gong WEI
魏和功 He Gong WEI
Year of Graduation: Jul 2011
Ph.D. Dissertation: Design of High-Speed Power/Area Optimized Multi-Bit/Cycle SAR ADC
Current Appointment: Design Engineer at Silicon Labs, Los Angeles, California, USA and former Post-Doc in the Communication Circuits Lab, Electrical Engineering Department, University of California Los Angeles (UCLA), USA
  1. He Gong Wei, Scientific and Technological R&D Award (PhD Student), Macau Science and Technology Award 2012

    FDCT

     Oct-2012
  2. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Silk-Road Award (A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS)

    Digest of Technical Papers from IEEE International Solid-State Circuits Conference – ISSCC 2011

     [Awarded for best asian PhD student research in ISSCC (“World Chip Olympic”)] Feb-2011
  1. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, Analog to Digital Converter Circuit

    Granted Number: 201242261

    Application Number: 100107757

    Taiwan Patent

     Mar-2014
  2. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Delay Generator

    Granted Number: 201246793

    Application Number: 100116148

    Taiwan Patent

     Mar-2014
  3. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Cascade Analog to Digital Converting System

    Granted Number: 8,466,823

    Application Number: 13/198,856

    US Patent

     Jun-2013
  4. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Delay Generator

    Granted Number: 8,441,295

    Application Number: 13/289,229

    US Patent

     May-2013
  5. Sai Weng Sin, He Gong Wei, Li Ding, Yan Zhu, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption

    Granted Number: 8,427,355

    Application Number: 13/232,442

    US Patent

     Apr-2013
  1. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

    IEEE Journal of Solid-State Circuits

     Vol.47, no11, pp. 2763-2772 Nov-2012
  2. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC

    IEEE Transactions on CAS – Part II: Express Briefs

     vol. 57, Issue 8, pp. 607-611 Aug-2010
  3. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs

    Hindawi VLSI Design, Special Issue with "Selected Papers from the Midwest Symposium on Circuits and Systems

     vol. 2010, no. 1, pp. 1-8 Apr-2010
  4. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS

    IEEE Trans. on Circuits and System II – Express Briefs

     vol. 57, Issue 1, pp. 16-20 Jan-2010
  1. Zhijie Chen, Yang Jiang, ChenYan Cai, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application

    IEEE Asian Solid-State Circuit Conference – (A-SSCC)

     pp 257-260 Nov-2012
  2. Zhijie Chen, JIANG Yang, Chenyan Cai, He-Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application

    in IEEE Asian Solid State Circuits Conference (A-SSCC)

     Nov-2012
  3. Guohe Yin, He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 0.024mm2 4.9 fJ 10-Bit 2MS/s SAR ADC in 65 nm CMOS

    IEEE European Solid-State Circuits Conference – ESSCIRC 2012

     pp 377-380 Sep-2012
  4. Si-Seng Wong, U-Fat Chio, He Gong Wei, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators

    Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic")

     pp. 73-76 Nov-2011
  5. Seng-Pan U, Sai Weng Sin, Yan Zhu, U-Fat Chio, He Gong Wei, R. P. Martins, Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs

    Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011

     pp. 173-176 Nov-2011
  6. Zhijie Chen, Peng Zhang, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error

    IEEE Midwest Symposium on Circuits and Systems – MWSCAS

     pp. 1-4 Aug-2011
  7. Peng Zhang, Zhijie Chen, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC

    ", IEEE Midwest Symposium on Circuits and Systems – MWSCAS

     pp. 1-4 Aug-2011
  8. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS

    IEEE International Solid-State Circuit Conference (ISSCC),

     pp. 188-189 Feb-2011
  9. Guohe Yin, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications

    IEEE International Conference on Electronics, Circuits and Systems (ICECS)

     pp. 878-881 Dec-2010
  10. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation

    IEEE Asian Solid-State Circuits Conference – ASSCC 2010

     pp. 1-4 Nov-2010
  11. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H

    in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010

     pp. 218-221 Sep-2010
  12. Sai Weng Sin, He Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R. P. Martins, Franco Maloberti, On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator

    in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC)

     pp. 49-52 Nov-2009
  13. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Process- and Temperature- Insensitive Current-Controlled Delay Generator for Sampled-Data Systems

    in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

     pp. 1192-1195 Dec-2008
  14. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs

    in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

     pp. 1164-1167 Dec-2008
  15. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs

    in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2008

     pp. 642-645 Sep-2008
  16. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier

    ", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS)

     pp. 5-8 Aug-2008
  17. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

    in Proceedings of IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2008

     pp. 922-925 Aug-2008
  18. He Gong Wei, Chon-Kit Lai, Seng-Pan U, R. P. Martins, A 100MS/s Recycling 2-Step ADC Embedding Programmable Gain Amplification for DVB Satellite

    the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

     pp. 132-135 Aug-2007
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