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Li Ding, Seng-Pan U, 0.46mm2 4-db NF unified Receiver Front end chip

ST

65nm A 12-bit 160-Ms/s Passive Pipeline-SAR ADC Oct-2013
Li Ding, Seng-Pan U, 500M High Speed ADC

UMC

90n High Speed SAR ADC Oct-2013
Tan-Tan Zhang, Pui In Mak, Mang I Vai, Peng Un Mak, Man-Kay Law, Sio Hang Pun, Feng Wan, R. P. Martins, 15-nW Biopotential LPFs in 0.35-µm CMOS Using Subthreshold-Source-Follower Biquads with and without Gain Compensation

IEEE Transactions on Biomedical Circuits and Systems

Vol. 7, Issue 5, pp 690-702 Oct-2013
Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, 0.013 mm2, kHz-to-GHz-bandwidth, thirdorder all-pole lowpass filter with 0.52-to- 1.11 pW/pole/Hz efficiency

IET Electronics Letters

Vol.49, Issue 21, pp 1340-1342 Oct-2013
Shengling Wang, Min Liu, Xiuzhen Cheng, Zhongcheng Li, Jianhui Huang, Biao Chen, Opportunistic Routing in Intermittently Connected Mobile P2P Networks

IEEE Journal on Selected Areas in Communications

Vol. 31, Issue 9, pp 369-378 Sep-2013
Yanwei Jia, Pui In Mak, Conner Massey, R. P. Martins, Lawrence J. Wangh, Construction of a microfluidic chip, using dried-down reagents, for LATE-PCR amplification and detection of single-stranded DNA

Lab on a Chip

Issue 13, pp 4635-4641 Sep-2013
Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS

IEEE Journal of Solid-State Circuits

Vol. 48, Issue 9, pp 2154-2169 Sep-2013
Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Background Gain-Calibration Technique for Low Voltage Pipelined ADCs Based on Nonlinear Interpolation

IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS)

pp 665-668 Aug-2013
Ka-Meng Lei, Pui In Mak, Man-Kay Law, R. P. Martins, ASQED 2013 Best Paper Award (A 2.93 µW 8-bit Capacitance- to -RE Converter for Movable Laboratory Mice blood Pressure Monitoring)

International Society for Quality Electronic Design(ISQED)

Aug-2013
Wei-Han Yu, Chak-Fong Cheang, Pui In Mak, Weng-Fai Cheng, Ka-Fai Un, U-Wai Lok, R. P. Martins, A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware

IEEE Transactions on Circuits and Systems – II

Vol. 60, No. 8, pp. 462-466 Aug-2013
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