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调研组

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分类： 调研组 共计: 930
Tianlan Chen, Yanwei Jia, Cheng Dong, Jie Gao, Pui In Mak, R. P. Martins, Sub-7-second genotyping of single-nucleotide polymorphism by high-resolution melting curve analysis on a thermal digital microfluidic device

Lab on a Chip

 16, 743-752 Jan-2016
Chio-In Ieong, Pui In Mak, Mang I Vai, R. P. Martins, Sub-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform and Maxima Modulus Pair Recognition for Power-Efficient Wireless Arrhythmia Monitoring

Asia and South Pacific Design Automation Conference (ASP-DAC)

 Jan-2016
Chak Fong Cheang, Ka-Fai Un, Pui In Mak, R. P. Martins, Time-Domain I/Q-LOFT Compensator Using a Simple Envelope Detector for a Sub-GHz IEEE 802.11af WLAN Transmitte

Asia and South Pacific Design Automation Conference (ASP-DAC)

 Jan-2016
Mingzhong Li, Chio-In Ieong, Man-Kay Law, Pui In Mak, Mang I Vai, Sio Hang Pun, R. P. Martins, Sub-threshold VLSI Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques

Asia and South Pacific Design Automation Conference (ASP-DAC)

 Jan-2016
Jianwei Lui, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

 Issue 24, Issue 7, pp. 2603-2607 Jan-2016
Bo Wang, Man-Kay Law, S. Mohamad, A. Bermak, Best Design Award
 

Asia and South Pacific Design Automation Conference (ASP-DAC) (2016)

 Jan-2016
Mingzhong Li, Chio-In Ieong, Man-Kay Law, Pui In Mak, Mang I Vai, Sio Hang Pun, R. P. Martins, Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques

IEEE Transactions on VLSI Systems

 vol. 23, pp. 3119-3123 Dec-2015
Yaohua Zhao, Pui In Mak, Man-Kay Law, R. P. Martins, Improving the Linearity and Power Efficiency of Active Switched-Capacitor Filters in a Compact Die Area

IEEE Transactions on VLSI Systems

 vol. 23, pp. 3104-3108 Dec-2015
Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation

IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015

 pp.1-4 Nov-2015
Jianhui Huang, Y. Y. Yu, Jiu Jiang Wang, Wang Meng, Sio Hang Pun, Peng Un Mak, Mang I Vai, Parallel Design for Ultrasound Synthetic Aperture Imaging FPGA

TENCON IEEE Region 10 Conference Proceedings

 Nov-2015
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