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Xin Lu, Man-Kay Law, Yang Jiang, Xiaojin Zhao, Pui In Mak, R. P. Martins, A 4μm Diameter SPAD Using Less-doped N-Well Guard Ring in Baseline 65nm CMOS

IEEE Transactions on Electron Devices

 vol. 67, pp. 2223-2225 May-2020
Zeng Xiang, Ying Pang, Lei Wang, Chi-Kong Wong, Chi-Seng Lam, Man-Chung Wong, Design, control and comparative analysis of a LCLC coupling hybrid active power filter

IET Power Electronics (PEL)

 vol. 13, no. 6, pp. 1207 – 1217 May-2020
Shiheng Yang, Jun Yin, Pui In Mak, R. P. Martins, Chapter 24 Multiplying DLLs” in “Phase-Locked Frequency Generation and Clocking, Architectures and circuits for modern wireless and wireline systems

The Institution of Engineering and Technology, London, United Kingdom

 978-1-78561-885-7 May-2020
Wei-kun Chen, Zi-liang Wei, Yueming Gao, Željka Lučev Vasić, Mario Cifrek, Mang I Vai, Min Du, Sio Hang Pun, Design of Galvanic Coupling Intra-Body Communication Transceiver Using Direct Sequence Spread Spectrum Technology

IEEE Access

 vol. 8, pp. 84123–84133 Apr-2020
Xiaofei Ma, Yan Lu, Qiang Li, A Fully Integrated LDO With 50-mV Dropout for Power Efficiency Optimization

IEEE Transactions on Circuits and Systems II: Express Briefs

 vol. 67, no. 4, pp. 725–729 Apr-2020
Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ÄÓ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

CICC 2020

 Mar-2020
Nandini Viteea, Harikrishnan Ramiah, Pui In Mak, Jun Yin, R. P. Martins, A 3.15 mW +16.0 dBm IIP3 22 dB CG Inductively Source Degenerated Balun-LNA-Mixer with Integrated Transformer-Based Gate Inductor and IM2 Injection Technique

IEEE Transactions on VLSI systems

 vol. 28, pp. 700-713 Mar-2020
Ren Shen, Yanwei Jia, Pui In Mak, R. P. Martins, Clip to release on amplification (CRoA): a novel enhancer for DNA amplification on and off microfluidics

Lab on a Chip

 20, 1928-1938, 2020 (Back cover) Mar-2020
Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration

IEEE Journal of Solid-State Circuits

 vol. 55, Issue 3, pp. 693-705 (invited special issue of CICC) Mar-2020
Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance

IEEE Journal of Solid-State Circuits

 vol. 55, No. 2, pp. 344-355 Mar-2020
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