A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS
Home/A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS
